
`include "common_header.verilog"

//  *************************************************************************
//  File : p8264_scr58_ptrngen.v
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized reproduction or use is expressly prohibited.
//  Copyright (c) 2008 MorethanIP
//  Muenchner Strasse 199, 85757 Karlsfeld, Germany
//  info@morethanip.com
//  http://www.morethanip.com
//  *************************************************************************
//  Designed by : Daniel Koehler; Thomas Schrobenhauser
//  info@morethanip.com
//  *************************************************************************
//  Description : Block Scrambler58 combined with 10G Test Pattern Generation.
// 
//  Version     : $Id: p8264_scr58_ptrngen.v,v 1.2 2016/07/13 06:58:13 dk Exp $
//  *************************************************************************

module p8264_scr58_ptrngen (
        reset,
        clk,
        clk_ena,
        en_gen_pat49,
        sel_pat,
        seed_1,
        seed_2,
        scrambler_bypass,
        data_in,
        data_in_type,
        data_out,
        data_out_type);

parameter OUT_REGISTER = 0;             // 1: implement output register; 0:combinatorial output (zero latency)

input           reset;                  //  active high reset
input           clk;                    //  clock
input           clk_ena;                //  clock enable
input           en_gen_pat49;           //  Enable 10G Test pattern generator (49.2.8) 
input           sel_pat;                //  Select pattern : 1 => 00 / 0 => Local Fault 
input   [57:0]  seed_1;                 //  Seed 1
input   [57:0]  seed_2;                 //  Seed 2
input           scrambler_bypass;       //  Bypass the Tx PCS scrambler in order to assist rapid synchronization following low power idle (FEC74).

input   [63:0]  data_in;                //  input data
input   [1:0]   data_in_type;           //  Data Block type (10: data / 01: control)
output  [63:0]  data_out;               //  Scrambled output data
output  [1:0]   data_out_type;          //  Data Block type (10: data / 01: control)

// out wires

wire    [63:0]  data_out;
wire    [1:0]   data_out_type;

// local

wire    sw_reset;               //  sync reset
wire    seed_ld;                //  load seed                               
wire    [57:0] seed_out;        //  Seed out                                
wire    [1:0]  ptrn_out_type;   //  Data Block type (10: data / 01: control)
wire    [63:0] ptrn_out;        //  Data out to Scrambler                   

assign sw_reset = 1'b 0;        // unnecessary, reduce logic

// 49.2.8 Pattern Generator. Zero latency when disabled.
// ------------------------

gen_pat_10g U_GPAT (

        .reset          (reset),
        .sw_reset       (sw_reset),
        .clk            (clk),
        .clk_ena        (clk_ena),
        .en_gen_pat     (en_gen_pat49),
        .sel_pat        (sel_pat),
        .data_in_type   (data_in_type),
        .data_in        (data_in),
        .seed_1         (seed_1),
        .seed_2         (seed_2),
        .seed_ld        (seed_ld),
        .seed_out       (seed_out),
        .data_out_type  (ptrn_out_type),
        .data_out       (ptrn_out));

// Scrambler
// ---------

scramble58seedl #(.OUT_REGISTER(OUT_REGISTER)) U_SCRMBL58 (

        .reset          (reset),
        .sw_reset       (sw_reset),
        .clk            (clk),
        .clk_ena        (clk_ena),
        .seed_ld        (seed_ld),
        .seed           (seed_out),
        .scrambler_bypass(scrambler_bypass),
        .din            (ptrn_out),
        .data_in_type   (ptrn_out_type),
        .dout           (data_out),
        .data_out_type  (data_out_type) );


endmodule // p8264_scr58_ptrngen
